Memory-Hierarchy-Design---Part-2--Ten-advanced-optimizations-of-cache-performance-教程.pdfVIP

Memory Hierarchy Design - Part 2. Ten advanced optimizations of cache performance John L. Hennessy, Stanford University, and David A. Patterson, University of California, Berkeley - October 01, 2012 Editors Note: Demand for increasing functionality and performance in systems designs continues to drive the need for more memory even as hardware engineers balance the dynamics of system capability, power, and cost against the growing performance gap between processor and memory. Architectures based on memory hierarchy address these issues, and what better source for the details of this approach than an excerpt on the subject from the seminal book on Computer Architecture by John Hennessy and David Patterson. Part 1, Basics of Memory Hierarchies looked at the key issues surrounding memory hierarchies and set the stage for subsequent installments addressing cache design, memory optimization, and design approaches. This installment, Part 2, reviews ten advanced optimizations of cache performance. Adapted from Computer Architecture, Fifth Edition: A Quantitative Approach by John Hennessy and David Patterson (Morgan Kaufmann) 2.2 Ten Advanced Optimizations of Cache Performance The average memory access time formula above gives us three metrics for cache optimizations: hit time, miss rate, and miss penalty. Given the recent trends, we add cache bandwidth and power consumption to this list. We can classify the ten advanced cache optimizations we examine into five categories based on these metrics: 1. Reducing the hit time - Small and simple first-level caches and way-prediction. Both techniques also generally decrease power consumption. 2. Increasing cache bandwidth - Pipelined caches, multibanked caches, and nonblocking c