半导体制备技术简介CH13.ppt

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm Chapter 13Process Integration Objectives List three isolation methods Describe sidewall spacer process and application Explain the VT adjustment implantation Name three conductors used for MOSFET gate List three metals used for interconnection process List basic steps for copper metallization process Identify the material most commonly used as final passivation layer for an IC chip Introduction It takes up to 30 masks and several hundreds process steps to finish an IC chip fabrication. Every step is related to other steps. CMOS processes Front-end: well formation, isolation, and transistor making Back-end Interconnection and passivation Wafer Preparation CMOS IC chips commonly used 100 wafer Bipolar and BiCMOS chips usually use with 111 wafers orientation. 1960 to mid-1970s, mainly PMOS, n-type wafer After mid-1970s, mainly NMOS, p-type wafer CMOS developed from NMOS process, for historical reason more fabs use p-type wafer NMOS and CMOS Processes The simplest NMOS IC processing had five mask steps: activation, gate, contact, metal, and bonding pad The early CMOS IC processing added three more mask steps: n-well (for p-type substrate), activation, gate, n-source/drain, p-source/drain, contact, metal, and bonding pad Both processes used p-type wafers NMOS CMOS of the Early 1980s Epitaxy Silicon Layer Bipolar transistors and BiCMOS chips require epitaxial silicon layer to form a buried layer Some power devices even require wafers made by floating zone method When CMOS chip speed is not very high, it doesn’t need the epitaxy layer High-speed CMOS chips need epitaxy layer Epitaxy Silicon Layer Silicon wafers made by the CZ method always have some oxygen because quartz crucible Oxygen can reduce carrier lifetime and slow down the device The epitaxy silicon layer creates an oxygen-free substrate and help to achieve high device speed Epitaxy Silicon Layer RCA clean to remove contaminants Anhydrate HCl dry