非常经典 清华大学 李宇根 PLL讲义 Lecture12.pdfVIP

Spring Semester, 2008 PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 12) Woogeun Rhee Institute of Microelectronics Tsinghua University Term Project • Design 645MHz fractional-N PLL circuit: - fref = 40MHz, fout = 645MHz with 50% duty cycle - Due date: June 24th 40MHz 645MHz (1) fref (3) (5) (6) (2) PFD CP VCO 2 fout (4) PLL BW: ~500kHz 16/17 k-bit ACCUM 2 W. Rhee, Institute of Microelectronics, Tsinghua University Term Project (continued) • Do followings: 1. Design loop filter for ~500kHz PLL bandwidth. 2. Draw open-loop gain Bode plot based on LPF design from (a). 3. Plot node 3, 4 and check the lock time. 4. Plot node 1, 2 after PLL is fully settled. What is the amount of static phase offset? 5. Plot node 5, 6 for 10 VCO cycles (i.e. zoom-in plot). 6. Estimate the spur level based on VCO gain and waveform at node 3. 7. Verify (f) result by having FFT and measure spur level at VCO output in dBc. E1. Plot eye diagram of VCO output and measure jitter in time domain. (extra) E2. Run phase noise simulation o