A HWSW Partitioning Algorithm for Dynamically Reconfigurable Architectures.pdfVIP

* A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures Juanj o Noguera, Rosa M. Badia Dept. Computer Architecture. Universitat Politecnica Catalunya e-mail: {j noguera, rosab}@ac.upc.es Abstract Traditionally, the HW/SW partitioning problem and the reconfiguration latency minimization problem (the maj or “System-On-Chip ” has become a reality, and recently challenge introduced by DRL devices) have been new reconfi gurable devices have appeared. However, f ew addressed independently. In this paper, we propose a eff orts have been carried out in order to defi ne H W/S W automatic HW/SW partitioning algorithm for DRL codesign methodologies and algorithms which address the architectures. The proposed algorithm takes into account challenges p resented by new reconfi gurable devices. the reconfiguration prefetching when performing HW/SW In this pap er we address this open problem and present partitioning. The experiments carried out demonstrate that a novel H W/S W pa rtitioning