FPGA门容量计算方法 xilinx.pdfVIP

APPLICATION NOTE  Gate Count Capacity Metrics for FPGAs XAPP 059 Feb. 1, 1997 (Version 1.1) Application Note Summary Three metrics are defined to describe FPGA device capacity: Maximum Logic Gates, Maximum Memory Bits, and Typical Gate Range. The methodology used to determine these values is described. Xilinx Family XC4000 Series, XC5000 Series Introduction Maximum Logic Gates Every user of programmable logic at some point faces the “Maximum Logic Gates” is the metric used to estimate the question: “How large a device will I require to fit my maximum number of gates that can be realized in the design?” In an effort to provide guidance to their users, FPGA device for a design consisting of only logic functions. Field Programmable Gate Array (FPGA) manufacturers, (On-chip memory capabilities are not factored into this met- including Xilinx, describe the capacity of FPGA devices in ric.) This metric is based on an estimate of the typical num- terms of “gate counts.” “Gate counting” involves measuring ber of usable gates per configurable logic block (CLB) or logic capacity in terms of the number of 2-input NAND logic cell multiplied by the total number of such blocks or gates that would be required to implement the same num- cells. This estimate, in turn, is based on an analysis of the ber and type of logic functions. The resulting capacity esti- architecture of the logic block and empirical data obtained mates allow users to compare the relative capacity of by comparing the implementation of en