基于FPGA的WALLACETREE乘法器设计.pdfVIP

20118 15 Aug.2011 34 16 Modern Electronics Technique Vol.34 No.16 基于FPGA 的WALLACE TREE 乘法器设计 王良全, 黄世震 ( , 　350002) 　:为了使基于 FPGA 设计的信号处理系统具有更高运行速度和具有更优化的 路版图布局布线, 提出了一种适 用于FPGA 结构的改进型 ALLACE TREE 架构乘法器。 首先讨论了基于标准单元3 ∶2压缩器的改进型6 ∶4压缩器, 根 据FPGA 中slice的结构特点通过在FPGA Editer 软件工具编辑, 对该压缩器进行逻辑优化, 将其应用于 FPGA 的基本单元 slice结构中。 并对乘法器的其他部分结构优化整合, 实现一个资源和性能达到合理平衡, 且易于在 FPGA 中实现的乘法器。 实际运行结果表明, 该乘法器的关键路径延时小于8.4 ns, 使乘法器时钟频率和系统性能都得到很大提高。 :乘法器; ALLACE;FPGA;6 ∶4 压缩器 :TN710-34　　　　　:A　　　　　:1004-373X(2011)16-0113-03 Design of Wallace Tree Multiplier Based on FPGA ANG Liang-quan, HUANG Shi-zhen (Fujian Key Laboratory of MicroelectronicsIntegratedCircuits, Fuzhou University, Fuzhou 350002, China) Abstract:In order to make the signal process system based on FPGA have faster runing speed and more optimized circuit in placement routing, a improved allace Tree multiplier applied to FPGA is brought forward.The6:4 compressor based on standard 3:2 compressor isdiscussed.The logicoptimization of thecompressor wasconductedwith FPGA editer tool, ac- cording to the structural characteristicsof Slice in FPGA.Other partsof the multiplier wasalso optimized.It made resource and function balanced, and iseasy to be realized in FPGA.The resultsobtainedfrom actual running show that this multiplier sdelay of key routing is less than 8.4 ns, which improves the clockfrequency of the multiplier and the system performance. Keyw ords:Multiplier; ALLACE;FPGA;6:4 compressor 　　, CSA(Carry Save Adder) 1 [1] 。 , “ ·”, 。FPGA 。