Technology Decomposition for LowPower Synthesis y.pdfVIP

Technology Decomp osition for LowPower Synthesis y Ra jendran Panda and Farid N Na jm Co ordinated Science Lab oratory University of Illinois at UrbanaChampaign Urbana IL Abstract where P y is the probability of the Bo olean dif x i Technology decomp osition and technology mapping ference of y with resp ect to x Therefore more judi i are two p oten tial stages for minimizing circuit p o wer cious choices for internal functional blo cks based on during logic syn thesis Since p o wer in CMOS circuits will bydesign give less active and lowerp ower cir is directly dep enden t on the extent of circuit switching cuits This idea is the basis of our work on lowp ower activity we presen t a no vel pro cedure to construct a synthesis While it is imp ortant to attack the synthe lo wactivity circuit structure in the technology decom sis problem at all levels in this pap er we fo cus on the p osition stage This would result in lo wp ower circuits technology decomp osition step and prop ose a new al when mapp ed The algorithm uses the transition den gorithm that achieves lower p ower circuits on a variety sity as a measure of switching activity and is applicable of test cases with little area or delay p enalty to b oth synchronous and asynchronous static circuits Our results sho w