《A Fast Exploration Procedure for Analog High-Level Specification Translation 》.pdfVIP

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 8, AUGUST 2008 1493 Short Papers A Fast Exploration Procedure for Analog High-Level Specification Translation Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan Mandal, and Amit Patra Abstract—This paper presents an exploration procedure for mapping given functional specifications of an analog system to the specification parameters of individual component blocks of the system topology. A meet-in-the-middle approach has been followed for constructing the fea- sible design space. It is constructed as the intersection of an application- bounded specification space and a circuit-realizable specification space. The least squares support vector machine principle is used to accurately identify the actual geometry of the feasible design space. The reduced design space speeds up the exploration procedure. The benefit of our methodology is the ability to obtain practically correct circuit-level spec- ifications of the component blocks of the system in a single pass. The effectiveness of the procedure has been demonstrated by considering a complete system. The simulation results satisfy the desired specifications of the system, validating the overall procedure. Fig. 1. High-level specification translation procedure. Index Terms—Design space description, design space exploration (DSE), high-level specification translation, least squares support vector machine elimination principle. Identification of the entire range of feasible (LS-SVM). performance values for