Synopsys 实验系列4_编译与优化_Design Compiler.ppt

Unit Summary ASIC of SYSU Appendix 1.综合中的分割 2.多时钟多周期设计 3.物理设计或版图所需的DC输出数据 ASIC of SYSU Appendix 1 Partitioning for Synthesis ASIC of SYSU 大规模的设计需要分割开子模块，如何分割将影响到DC综合的结果 本章目的： 简单了解设计的分割方法 Poor Partitioning ASIC of SYSU Better Partitioning ASIC of SYSU Best Partitioning ASIC of SYSU 该处在综合时把输入逻辑与D触发器优化成某一类触发器 Appendix 2 More Clock/Cycle Designs ASIC of SYSU 同步多时钟约束 异步多时钟约束 多周期路径约束 多路径约束 Appendix 3 Data Needed for Physical Design or Layout ASIC of SYSU * * * ※ 4-8 Setup Slack ※ 4-9 Data Required Time - Hold ※ 4-10 Hold Slack ※ 4-11 Hold Slack 注意： Data Arrival Time和 Data Required Time 与Setup Slack中的同名有所区分 Unit 4 Agenda Company Logo Setup Time and Hold Time Setup-Timing Constraints Specifying an Area Constraint Specifying Setup-Timing Constraints Objective: 定义时序电路中各种路径的setup-timing约束 1. All input logic paths (starting at input ports) 2. The internal (register to register) paths 3. All output paths (ending at output ports) Under the following conditions: 1. 你已经知道设计的细则 2.模块或者芯片级的设计 3.单个时钟，单个周期 ASIC of SYSU 在前端设计中一般不做hold-timing 约束 hold-timing 约束可以在后端修复 4-12 默认的设计方案 ASIC of SYSU 该设计为：单时钟，同步设计 三种常见路径约束： 1.Reg-to-Reg Paths 2.Input Paths 3.Output Paths …… 4-13 Constraints Reg-to-Reg Paths: Example ASIC of SYSU Tmax = Period - Setup_Time (assuming 0 clock skew) = 2 – 0.2 = 1.8 ns 4-14 Modeling Clock Skew(偏斜) ASIC of SYSU 时钟偏斜：相连的两个寄存器如 FF1与FF2的clock到达时间的偏差 4-15 set_clock_uncertainty and Setup Timing ASIC of SYSU 由于时间的不确定因素，setup timing 的最坏的情况： FF2的时间早到0.14ns，setuptime 为 0.08， FF2的输入口 D需要在2-0.14-0.08=1.78ns时有稳定数据 4-16 Modeling Latency ASIC of SYSU set_clock_latency 默认情况下代表：Network Latency 4-17 Modeling Transition Time(瞬变时间) ASIC of SYSU 4-18 Constraining Input Paths: Example 1 ASIC of SYSU Tmax = Period - Input Delay - Setup_Time (assuming 0 clock skew) = 2 – 0.6 - 0.2 = 1.2 ns 4-19 Constraining Input Paths: Example 2 ASIC of SYSU -preriod 2.5 -max 0.9 –clock Clk [get_ports A] 4-20 Constraining Output Paths: Example 1 A