一种专用可重配置的FPGA嵌入式存储器模块的设计与实现_余慧.pdfVIP

2 Vol .40 No . 2 20 12 2 ACTA ELECTRONICA SINICA Feb. 2012 FPGA 余 慧, 王 健 ( , 200433) : FPGA . 8 , 18Kbits BRAM, 16K @ 1bit8K @ 2bits4K @ 4bits2K @ 9bits1K @ 18bits512@ 36bits ;write- irstno- change . BRAM FPGA . BRAM FPGA . SMIC 0113Lm 8 CMOS , FDP- II , 415mm@ 414mm . March C+ MBIST , , FDP- II BRAM , , . : ; ; FPGA; ; : TP33814 : A : 0372- 2112 ( 2012) 02- 0215- 08 URL: http: / / www . ejournal. org. cn DOI: 10 . 3969/ j. issn . 0372- 2112 . 2012. 02. 002 The Design and Implement of a Special Reconfigurable FPGA Embedded BRAM YU Hui, WANG Jian ( ASI C and System State K ey laborat ory , Fudan University , Shanghai 200433, China) Abstract: A customized recon igurable embedded Block RAM module or FPGA chip is propo sed . The number o BRAM is eight and each module is a synchronous dua-l port memory cell w ith the capacity o 18Kbits. The BRAM can be con igured as six bit w idth modes including 16K @ 1bit8K @ 2bits4K @ 4bits2K @ 9bits1K @ 18bits512@ 36bits; tw o write modes such as write- irst no- change. Several BRAM can be cascaded thro ugh interconnect circuit to achieve the expansion in depth or w idth. This paper o- cuses on the circuit that can realize the recon iguration unction . SMIC 0 . 13um 8- layer metal CMO S process is applied to produce the complete layout o FDP-II chip and then tape- out. The chip area is about 4. 5mm @ 4. 4mm and tested by cooperating w ith its so tw are system w hich applies M arc