DSP + FPGA Supervisory Communications Infrastructure.pptVIP

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2015-11-13 发布于安徽
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DSP + FPGA Supervisory Communications Infrastructure.ppt

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DSP + FPGA Supervisory Communications Infrastructure.ppt

m-haney@uiuc.edu 22aug01 DSP + FPGA Supervisory Communications Infrastructure with possible implications/applications 22 Aug 2001 M. Haney, University of Illinois Pixel (Muon) Trigger Supervisor Monitor (P/M)TSM Control Functions: Initialization sets the maximum bandwidth necessary can not take all day... Command Parsing and Distribution to subordinates, from RunControl Error Response autonomous, “local” (regional) not to be confused with higher-level driven Error Handling, which appear as “Commands” (P/M)TSM (continued) Monitor Functions Error Message Collection and Reporting organized, formatted, sent higher up Hardware and Software Status not unlike Error Messages... Status and Data Histogramming utilizes remaining (P/M)TSM system bandwidth Close-up: FPGA Close-up: DSP Factoids ARCNet 2.5 Mbps, 255 nodes (max), 500 byte packets (max), broadcast capability, “easy” TMS320C67x DSP ~70 Kbyte internal RAM, ~1200 MIP fixed/floating point TMS320C64x DSP ~1 Mbyte internal RAM, ~3x faster… fixed point only More Factoids Host Port Interface (TI DSP only) almost-direct access into the DSP peek, poke uses DMA (like) resources… (concept not unique to TI) DMA crossing data in Buffered Serial Port(s) opinions out; dual, ~75Mbps (C6x) DSP/BIOS (Texas Instruments) based on SPOX “the oldest DSP RTOS…” scalable real-time kernel small footprint ( 2Kw) preemptive multithreading scheduling (tasks, soft/hard interrupts) synchronization (between tasks, interrupts) hardware abstraction extensible DSP/BIOS (continued) real-time analysis real-time instrumentation explicit API calls (controllably) implicit, at context changes host-target communications statistics gathering same as above host data channels binds kernel I/O objects to host files RTDX - Real Time Data Exchange utilizes JTAG chain (and emulation bits) target (kernel) component moves messages to/from DSP/BIOS queues from/to JTAG-accessible buffer “real time” target to host (?) host component data visualization and anal