新数字设计基础 双语教学版 教学课件 英Barry Wilknson 双语课件（第9章）.pptVIP

* 在线教务辅导网： 教材其余课件及动画素材请查阅在线教务辅导网 QQ:349134187 或者直接输入下面地址： 9. Introduction to VHDL 9.1 A simple example in VHDL 9.2 Stylistic issues 9.3 The IEEE library 9.4 Conditionals in VHDL 9.5 Handling multi-bit signals 9.1 A simple example in VHDL 1. Entity We will start off with a NAND gate. The first thing is to say what the device looks like to the outside world. This basically means describing its port map, i.e. the signals that flow in and out of it. 9.1 A simple example in VHDL To describe this in VHDL, we use an entity declaration. ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END; Each of the signals in the port map is declared as having a mode and a type. The mode can be IN or OUT, and simply says whether the signal is an input or an output. 9.1 A simple example in VHDL The type STD_LOGIC represents a signal that bit can a value of ‘0’, ‘1’, ‘X’ or ‘U’. STD_LOGIC is the normal way to describe logic signals that appear at the input or output of gates, or at wires in between them. ‘X’ means unknown ‘U’ means uninitialized, i.e. a signal that has not yet been assigned any valid logical value. 9.1 A simple example in VHDL 2. Architecture Now that we have described the inputs and outputs, we need to say what the device does, i.e. how its outputs respond to its inputs. ARCHITECTURE simple OF nandgate IS BEGIN c = a NAND b; END; The ARCHITECTURE statement says what goes on inside nandgate. 9.1 A simple example in VHDL After the ARCHITECTURE statement comes the word BEGIN. This introduces the main body of the architecture, which explains how the outputs relate to the inputs. At the end of the body comes the END statement, which says that we have reached the end of the body. How the outputs relate to the inputs is described by c = a NAND b; The symbol = means that the signal c gets the value of a NANDed together with the value of b. Whenever a or b change their value, this statement causes the value of c t