新数字设计基础 双语教学版 教学课件 英Barry Wilknson 双语课件（第11章）.pptVIP

* 在线教务辅导网： 教材其余课件及动画素材请查阅在线教务辅导网 QQ:349134187 或者直接输入下面地址： 11. VHDL simulation 11.1 Simulation 11.2 VHDL simulation of dataflow code 11.3 Simulation of structural VHDL 11.4 The uninitialized logic value 11.5 Delay modeling 11.6 Test benches 11.1 Simulation VHDL descriptions must be simulated to confirm that they behave as required. Simulation allows us to apply inputs, and then trace how the rest of the circuit evolves with time as the influence of the new inputs propagates through towards the outputs. We can then compare the predicted outputs for our design to the desired outputs. If there are no differences then we can conclude that our design is correct. 11.2 VHDL simulation of dataflow code Event A change to a signal that is scheduled to take place at a certain time is called an event. The VHDL simulation proceeds by manipulating an event queue. Event queue A VHDL statement only executes when a value on the RHS changes. 1. Some terms on simulation 11.2 VHDL simulation of dataflow code The VHDL description of a full adder ARCHITECTURE number3 OF fulladd IS SIGNAL n1, n2, n3, n4: STD_LOGIC; BEGIN n1 = x XOR y; -- Statement 1 sum = cin XOR n1; -- Statement 2 n2 = x AND y; -- Statement 3 n3 = cin AND x; -- Statement 4 n4 = y AND cin; -- Statement 5 cout = n2 OR n3 OR n4; -- Statement 6 END ARCHITECTURE number3; 2. Example for simulation 11.2 VHDL simulation of dataflow code Assumed that all signals are initially at zero. Time = 0 It has a list of the present value for each signal, any new value that has been scheduled to take place in future, and the time at which the signal must assume this new value. 3. Process for simulation 11.2 VHDL simulation of dataflow code All statements 1-6 are scanned simultaneously. The event on x triggers the execution of the statements: n1 = x XOR