混合信号SOC测试方法与实践.pdfVIP

摘要 摘 要 随着集成电路制造技术的快速发展，测试变得越来越复杂、越来越困难也越来越 重要。在 SOC 的可测性设计中，混合信号电路测试和真速测试是 SOC 测试遇到的新 挑战。 本文通过对 SOC 测试方法和标准的研究，提出一种基于嵌入式处理器的 SOC 真 速测试方案与数模混合电路核测试方案。该方案可以减少测试成本，提高测试速度。 数模混合测试信号生成的设计运用直接数字频率综合技术和 Σ-△调制方法。通过振 荡方法产生数字正弦波，运用过采样方法降低量化噪声，使用片上资源少，产生波形 精度高。针对真速测试，本文设计总线监视模块。该模块为基于处理器真速测试SOC 核的设计方法提供了有力的保障，并通过自制的验证板，验证总线监视模块的功能。 在设计工作中，注重利用现有SOB成熟测试思想和技术积累；同时针对SOC测试 面临的新问题探索，创新和实践。使用数学软件，硬件编程语言，可编程器件和EDA 工具作为开发手段，最终完成预定的设计目标和要求。 关键词：测试 SOC 数模混合 真速 I 万方数据 摘要 ABSTRACT With the fast development of IC manufacturing techniques, test is gradually becoming more and more complicated, difficult and important. In the design for SOC(System on a Chip) test, mixed-signal circuit test and at-speed test are new challenges. After studying the SOC test method and test provisional standard, a scheme based on embedded processor satisfying at-speed test environment is proposed to test mixed-signal SOC IP core. This method can reduce test time and hardware cost. A suitable signal source generator module generates sinusoidal signal based on direct digital frequency synthesis techniques (DDFS) and delta-sigma (Δ-Σ) modulation technique. It can decrease on-chip test portion and generate precise wave using over-sampling technology. The author also designs a bus monitor module in this paper that can help to accomplish at-speed test and an experiment board is designed to verify the function of this module. In this paper, some ideas and practices are used to solve new question in SOC test. The