《VerilogHDL8层全自动电梯控制》.docx

（一）状态主控模块设计： (1)、信号定义说明： Clk: 同步时钟信号脉冲； f1,f2,f3,f4,f5,f6,f7,f8： 楼层请求及选择信号； sf1,sf2,sf3,sf4,sf5,sf6,sf7,sf8： 楼层状态显示； door: 开门指示信号； floor: 送数码管显示的当前楼层数； deals: 请求信号预存； up: 上行信号； down: 下行信号； Count: 计数信号寄存； (2)、自动控制源程序： Module control(clk,f1,f2,f3,f4,f5,f6,f7,f8,sf1,sf2,sf3,sf4,sf5,sf6,sf7,sf8,door,floor，up,down); input clk,f1,f2,f3,f4,f5,f6,f7,f8; output sf1,sf2,sf3,sf4,sf5,sf6,sf7,sf8,door,floor,up,down; reg sf1, sf2,sf3,sf4,sf5,sf6,sf7,sf8,door,up,down; reg[8:1]deals; reg[2:0]count; reg[3:0]low,high,floor; always@(posedge clk) begin if(f1) begin deals[1]=1;door=1; if(low1||low==4b0)low=1; end if(f2) begin deals[2]=1; door=1; if(high2{f3,f4,f5,f6,f7,f8}==6b0) high=2; if((low2||low==4b0)!f1) low=2; end if(f3) begin deals[3]=1; door=1; if(high3{f4,f5,f6,f7,f8}==5b0) high=3; if((low3||low==4b0){f1,f2}==2b00) low=3; end if(f4) begin deals[4]=1; door=1; if(high4{f5,f6,f7,f8}==4b0) high=4; if((low4||low==4b0){f1,f2,f3}==3b0) low=4; end if(f5) begin deals[5]=1; door=1; if(high5{f6,f7,f8}==3b0) high=5; if((low5||low==4b0){f1,f2,f3,f4}==4b0) low=5; end if(f6) begin deals[6]=1; door=1; if(high6{f7,f8}==2b00) high=6; if((low6||low==4b0){f1,f2,f3,f4,f5}==5b0) low=6; end if(df7) begin deals[7]=1; door=1; if(high7!d8) high=7; if((low7||low==4b0){f1,f2,f3,f4,f5,f6}==6b0) low=7; end if(f8) begin deals[8]=1; door=1; if(high8) high=8; end if({sf1,sf2,sf3,sf4,sf5,sf6,sf7,sf8}==8b0) begin {sf1,sf2,sf3,sf4,sf5,sf6,sf7,sf8}=8 floor=1; end else if(count==3b110) begin count=0;door=0; if(low==floor) low=4b0000; if(high==floor)