《数字电子技术_英文版_chapter07》.pptVIP

7INTRODUCTION TOPROGRAMMABLE LOGIC DEVICES可编程逻辑器件 7-1 PLD ARRAYS AND CLASSIFICATIONSPLD阵列和分类 What’s PLD? PLD is abbreviated from “programmable logic device”. A PLD consists of a large array of AND gates and OR gates that can be programmed to achieve specified logic functions. PLDs, particularly PAL and GAL devices, can be used to replace SSI and MSI logic devices in most types of applications, resulting in fewer parts and lower cost. Programmable Arrays All PLDs consist of programmable arrays. A programmable array is essentially a grid of conducts that form rows and columns with a fusible link at each cross point. The OR Array（或阵列） This type of array consists of an array of OR gates connected to a programmable matrix with fusible links at each cross point of a row and column. The array is programmed by blowing fuses to eliminate selected variables from the output functions. The AND Array（与阵列） This type of array consists of an array of AND gates connected to a programmable matrix with fusible links at each cross point. The array is programmed by blowing fuses to eliminate selected variables from the output functions. Classification of PLDs Programmable Read-Only memory (PROM) 可编程只读存储器 Programmable Logic Array (PLA), aka, FPLA 可编程逻辑阵列 Programmable Array Logic (PAL) 可编程阵列逻辑 Generic Array Logic (GAL) 通用阵列逻辑 PROM The PROM consists of a set of fixed (nonprogrammable) AND gates as a decoder and a programmable OR array. The PROM is used primarily as an addressable memory and not a logic device because of limitations imposed by the fixed AND gates. PLA The PLA consists of a programmable AND array and a programmable OR array. PAL The PAL consists of a programmable AND array and a fixed OR array with output logic. The PAL is the most common one-time PLD and is implemented with bipolar technology (TTL or ECL). GAL The GAL consists of a programmable AND array and a fixed OR array with programmable output logic. The main differences between GAL and PAL a