高性能运动估计的架构设计和优化的研究.pdf

摘 要 可降低运动估计的计算复杂度，从而实现低功耗省资源两个要求；后者 能避免不必要的外存访问，从而降低数据带宽。实现结果表明，相比同 类设计，所提设计以少量吞吐率损失换取面积效率和功耗效率明显改善。 关键词：运动估计 可变块大小 脉动阵列 低功耗 低带宽 大规模集成电路 II ABSTRACT ABSTRACT Block matching motion estimation which is adopted widely in mainstream video compression standards is used to reduce the bit-rate in video compression systems by exploiting the temporal redundancy between successive frames. For practical realization of video encoder for consumer products, e.g. mobile multimedia phone, it is desirable that the video encoder can compress video frames within certain pre-allocated computational budget as the computational power of these consumer products would be limited. This underlines the need for high-speed low-power silicon processing architectures for implementing video compression algorithms at different levels of resolution. Generally, motion estimation computing array (MECA) performs up to 50% of computations in the entire video coding system, and is typically considered the computationally most important part of video coding systems. Thus, integrating the MECA into a system-on-chip design has become increasingly important for video coding applications. Intensive study of efficient (high-throughput, low power, low bandwidth) architecture of motion estimation is conducted in this doctoral dissertation. The main work and innovation are listed as follows: 1) An area-efficient low bit-depth representation based full search block motion estimation engine is proposed to meet the processing requirements of real-time low-co