ABCAIG,basics.ppt

* Electrical and Computer Engineering Electrical and Computer Engineering Archana Rengaraj ABC Logic Synthesis basicsECE 667 Synthesis and Verification of Digital SystemsSpring 2011 Overview Introduction Previous synthesis methods ABC synthesis And-Inverter Graphs (AIG) representation AIG canonicity and redundancy AIG construction NPN equivalence AIG transformations Rewriting ABC commands Summary Introduction Synthesis of a design Conversion of abstract form of desired circuit behavior into a form of logic gates Processing combinational logic before technology mapping technology independent optimization Technology dependent optimization Synthesis targeting ASICs and FPGAs SIS Synthesis Previous systems for logic synthesis and optimization: SIS, VIS – Verification Interacting with Synthesis, MVSIS - Multi valued SIS Drawbacks of these systems Cannot integrate technology mapping and retiming Inefficient for large circuits Areas of improvement quality and runtime of synthesis and verification SIS Synthesis algorithm Traditional combinational synthesis steps sweep – removing redundant nodes eliminate, resubstitute - finding better logic boundaries fast_extract – detect shared logic simplify, full_simplify – optimization of nodes ABC synthesis Representing logic in terms of And Inverter Graphs (AIG) Difference from SIS systems simple data structure: Two-input ANDs and Inverters Transformation of network done by rewriting AIGs Advantages: scalable, faster, uniformity in computation, better quality after technology mapping ABC applications synthesis and verification? combinational and sequential synthesis combinational and sequential equivalence checking And-Inverter Graphs representation Boolean network converted to AIG using De Morgan law AIG NAND – Inv representation f = (x1’.x3’)’. x2 f = [(x1.x2)’.(x2.x3)’]’ f = x1*x2 + x2*x3 AIG canonicity AIGs are not canonical sa