ANewKindofAlgebra-ECEn224.pptVIP

Initial State When a sequential circuit is powered on, we have no guarantee it will start in any particular state We must make sure our counters don’t start in an invalid state They could remain stuck in invalid states! Most digital systems have a reset signal that is asserted after power up Designers must use flip flops with reset/set inputs as needed to achieve desired startup behavior 13 COUNTERS Page * ECEn 224 Example Problem Design a 3-bit binary counter The Z output is TRUE iff count value is even The Y output is TRUE iff count value is multiple of 3 ECEn 224 ? 2003-2008BYU 13 COUNTERS Page * ECEn 224 COUNTERS Counters Transition Tables Moore Outputs Counter Timing 13 COUNTERS Page * ECEn 224 General Sequential Systems D Q D Q CurrentState StateMemory InputFormingLogic NextState 13 COUNTERS Page * ECEn 224 A Sequential Counter CLK NextState 01 10 11 00 01 CurrentState 00 01 10 11 00 The current stateloads the nextstate values inresponse to the clock edge. IFL reacts after some gate delaysto produce a newnext state. Clock edges… D Q D Q CurrentState StateMemory +1 NextState 2 Master Master Master Master Master Slave Slave Slave Slave 13 COUNTERS Page * ECEn 224 Transition Table for 2-Bit Counter It is the truth table for the input forming logic… It describes what the next state values are as a function of the current state (clock is assumed) 13 COUNTERS Page * ECEn 224 Implementation of 2-Bit Counter Q0 Q1 D Q D Q CLK CLK N1 N0 N0 = Q0’ N1 =Q1 ? Q0 13 COUNTERS Page * ECEn 224 Example 2 – A Gray Code Counter N1= Q0 N0 = Q1’ Q1 D Q D Q Q0 CLK CLK N1 N0 13 COUNTERS Page * ECEn 224 Example 3 – Not All Count Values Used Desired count sequence = 00 – 01 – 11 - 00 … What should next state for 10 be? 13 COUNTERS Page * ECEn 224 Example 3 – Not All Count Values Used Do the normal K-map minimization with don’t cares N1 = Q0?Q1’ N0 = Q0’ 13 COUNTERS Page * ECEn 224 Example 4 – A Ring Counter Desired count sequence =