explicit gate delay model for timing evaluation - ispd.pptVIP

Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao : Motorola, Inc. Youxin Gao : Synopsys, Inc., Li-Pen Yuan : Synopsys, Inc., Li-Da Huang : University of Texas at Austin Seokjin Lee : University of Texas at Austin Thus we propose a new approach for the gate delay model. Our new approach has three following characteristics. The first one is our gate modeling work independent of its load. It makes it possible to pre-compute the gate model before the start of any timing analysis and synthesis, and then it is not needed to do the gate modeling again. And, the time-consuming calculation of the effective capacitance is totally unnecessary in the new model. This significantly speeds up the procedures of timing analysis, particularly in optimization loops. Based on the second characteristic, the gate model can be incorporated into the process of interconnect delay evaluation seamlessly. Since it is not necessary to decouple the gate with its interconnect analysis, we can do the timing analysis all the way from the gate input to the fan-out point and get the stage delay directly. the third characteristic certifies that this unified analysis keeps almost the same complexity as the original one since there are only several linear components being added into the timing analysis of interconnect. we construct the new gate model on a second-order circuit, which is shown in Figure. The reasons are: we notice that the foundations of these models are all built on a first-order $RC$ circuit and the inherent one-pole characteristic of this circuit makes it unable to fully fit with the non-linear output of a gate, particularly in the nowadays deep submicron technology. Thus, to compensate it, the driving source of model circuit has to be set to a time varying one, such as linear piecewise. The second gate model and last one are similar i