Impact of NBTI on SRAM Read Stability and Design for.pdfVIP

Impact of NBTI on SRAM Read Stability and Design for Reliability Sanjay V. Kumar, Chris H. Kim, and Sachin S. Sapatnekar Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 Abstract— Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in Static Noise Margin (SNM), which is a measure of the read stability of the 6-T SRAM cell has been estimated using Reaction-Diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique. Index Terms : Negative Bias Temperature Instability (NBTI), SRAM, Cache, Static Noise Margin (SNM), Reaction-Diffusion (R-D) Model. Fig. 1. Schematic description showing the generation of interface traps I. INTRODUCTION when a PMOS transistor is biased in inversion. Figure (i) shows the 3-D structure of S i at the S i S iO2 interface in the 111 crystal orientation. N