Multilevel Symmetry-Constraint Generation for Retargeting.pdfVIP

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 6, JUNE 2006 945 Multilevel Symmetry-Constraint Generation for Retargeting Large Analog Layouts Sambuddha Bhattacharya, Nuttorn Jangkrajarng, and C.-J. Richard Shi, Fellow, IEEE Abstract—The strong impact of layout intricacies on analog- In analog design, tradeoffs between the major design goals circuit performance poses great challenges to analog layout auto- like gain, bandwidth, stability, noise reduction, linearity, and mation. Recently, template-based methods have been shown to power minimization demand considerable effort and time from be effective in reuse-centric layout automation for CMOS ana- log blocks such as operational amplifiers. The layout-retargeting the designers. Recently, significant progress has been made in method first creates a template by extracting a set of constraints the area of optimization tools [1], [2] that automatically synthe- from an existing layout representation. From this template, new size analog circuits to meet desired performance specifications. layouts are then generated corresponding to new technology However, the electrical behavior of high-performance analog processes and new device specifications. For large analog layouts, designs is affected not only by the device sizes and biasing but however, this method results in an unmanageable template due to a tremendous increase in the number of constraints, especially those also by the layout styles and intricacies. emerging from layout symmetries. In this paper, we present a new Process and temperature v