Design Sensitivities to Variability Extrapolations and.pptVIP

Design Sensitivities to Variability: Extrapolations and Assessments in Nanometer VLSI Y. Kevin Cao*, Puneet Gupta+, Andrew Kahng+, Dennis Sylvester#, Jie Yang# *UC Berkeley EECS Dept. +UC San Diego ECE Dept. #U. Michigan EECS Dept. Introduction Why process variability is important now: Optical lithography: feature size limited by diffraction, starting with 0.35 μm generation Same patterns look the same? ITRS: one of the biggest challenges is Lgate control Affects both circuit’s performance and yield Motivation Necessity of Design Sensitivity Study Cost of corrections May be proportional to complexity of masks Not all corrections are implementable Previous studies Lacking quantified projections of variation in scaled technology Overly simplified circuit topologies and performance models Ignoring physical correlations Interpretation of Results Returns for alternative process improvements measured as Selling point yield Selling point: delay point which gives 99.7% parametric yield with all parameters varying nominally Required guardbanding 3?/mean is taken as the required guardbanding, assuming 99.7% to be the target parametric yield and the delay distribution to be Gaussian Contributes insights to the impact of process variation through the next two ITRS technology nodes Correlation Specification Vth0 = (Tox, Nch, Leff, and Xt) Perfect correlation between NMOS and PMOS within a gate Negative correlation between metal width and spacing variation as well as ILD and H variation Spatial correlation among devices and interconnect Correlation coefficient linear decays with distance Comparison with plots “No correlation coefficient model” is about 6% optimistic We could lose 14% more from the “perfect correlation model” Required Guardbanding The guardbanding value drops from 18.5% for 180nm to 13% for 70nm Effect of process control Leff control has the most impact Intense sensitivity to Vdd Selling Point Parametric Yi