7-3 同步状态机分析.pptVIP

Sequential Logic Circuit Analysis and Design(时序逻辑电路的分析和设计) Some state machine They all have clock generator They all change states when a ‘tick’ occurs. They all have memories 7.3 Clocked Synchronous State-Machine Analysis( 时钟同步状态机的分析)(P542) “State machine” is a generic name given to these sequential circuits; 状态机:时序电路的通称. “clocked” refers to the fact that their storage elements (flipflops)employ a clock input; 时钟: 存储元件的时钟输入. “synchronous” means that all of the flip-flops use the same clock signal. 同步:构成状态机的所有触发器都使用同一个时钟. 7.3.1 State-Machine Structure Next state = F(current state,input) Output = G(current state,input) 7.3.2 Output Logic A sequential circuit whose output depends on both state and input is called a Mealy machine. In some sequential circuits, the output depends on the state alone,Such a circuit is called a Moore machine. 7.3.3 Characteristic Equations(特征方程)(P545) Q*(next state) ,Q(current state) 7.3.4 Analysis of State Machines with D Flip-Flops(P545) The analysis of a clocked synchronous state machine has three basic steps: 1. Determine the next-state and output functions F and G. 2. Use F and G to construct a state/output table(状态输出表) that completely specifies the next state and output of the circuit for every possible combination of current state and input. 3. (Optional) Draw a state diagram that presents the information from the previous step in graphical form. Clocked Synchronous State-Machine Analsys BASIC steps： Write EXCITATION function F and OUTPUT function G GET TRANSITION FUNCION Q*=? USE Q*、G TO CONSTRUCT TRANSITION/OUTPUT TABLE DRAW STATE DIAGRAM AND WAVEFORM（OPTIONS） CHECK IF THE CIRCUIT CAN START BY ITESELF DESCRIBE THE FUNCTION OF THE CIRCUIT ANALYSISED State diagram A state diagram presents the information from the state/output table in a graphical format. It has one circle (or node) for each state, and an arrow (or directed arc) for each transition. Specification (说 明) 可以给每个状态命名 通常用S表示当前状态，S*