8-2 时序电路的设计 计数器.pptVIP

Review of the last class 8.4.3 MSI Counters and Applications4位二进制计数器74x163 Other MSI counters 1bit BCD counter 74x160 Synchronous clear 、 74x162 Asynchronous clear 74x160、74x162 the counting sequence is modified to go to state 0 after state 9. In other words, these are modulo-10 counters, sometimes called decade counters. the QD and QC outputs have one-tenth of the CLK frequency, they do not have a 50% duty cycle, and the QC output. Other MSI counters 74x169---up/down counter Timing diagram for a modulo-8 binary counter and decoder,showing decoding glitches. Modulo-m counter Use SSI device —— Clocked Synchronous State-Machine Design Use MSI counter —— using n bit binary counter as a modulo-m counter in two cases： m 2n m 2n using the ’163 as a modulo-11 counter(用4位二进制计数器74x163实现模11计数器) Modulo-m counter This circuit uses a NAND gate to detect state 10 and force the next state to 0. Notice that only a 2-input gate is used to detect state 10 (binary 1010). Although a 4-input gate would normally be used to detect the condition CNT10 = Q3 × Q2’ × Q1 × Q0’, the 2-input gate takes advantage of the fact that no other state in the normal counting sequence of 0–10 has Q3 = 1 and Q1 = 1. In general, to detect state N in a binary counter that counts from 0 to N, we need to AND only the state bits that are 1 in the binary encoding of N. using the ’163 as a modulo-11 counter A 74x163 used as an excess-3 decimal counter  74x163用作余3码计数器 Cascading 74x163s(计数器的级联) Modulo m counter（ m 2n） 先进行级联，再整体置零或预置数 例：用74x163构造模193计数器 两片163级联得8位二进制计数器（0～255） —— 采用整体清零法，0～192 —— 采用整体预置数法，63～255 256－193＝63 若 m 可以分解：m = m1?m2 分别实现m1和m2，再级联 What is the modulo of the circuit below? Verilog for 163 How many inputs and outputs? INPUT:clk,clr_l,ld_l,enp,ent,D,C,B,A OUTPUT:qa,qb,qc,qd,rco Pay attention: All is controled by clk 8.4.3 MSI Counters and Ap