Power On Sequencing-0909.pptVIP

Agenda Lily model-Olympus Block Diagram Power sequencing before press Power button Power sequencing after press Power button How System Work after power on Q? 1-1 VccRTC RTCRST# Timings 1-2 Adapter in - AD+ - DCBATOUT 1-3 DCBATOUT - AUX power 1-4 KBC generate S5_ENABLE 1-5 5V_S5 3D3V_S5 1-6 RSMRST# 3D3V_LAN_S5 2-1 PWRBTN# SLP_S5# 2-2 SLP_S5# inactive to generate 1D8V_S3 2-3 SLP_S5# inactive to generate1D5V_S3 2-4 SLP_S5# inactive to generate 0D75V_S3 for DDR3 2-5 5V_S0 3D3V_S0 1D5V_S0 Timings 2-6 SLP_S3# inactive to generate 1D8V_S0 2-7 SLP_S3# inactive to generate1D05V_S0 2-8 SLP_S3# inactive to generate 1D1V_S0 2-9 SLP_S3# inactive to generate VGA_CORE_S0 2-10 CPUCORE_ON 2-11 CPU_VCC_CORE 2-12 CK_PWRGD to CLK GEN 2-13 PM_PWROKCL_PWROK 2-14 PLT_RST# CPURST# 第*頁 動作原理淺談之Power On Sequencing NK0100 甘名勇/Andy Gan #5612 2008/09/09 Power On Sequencing Before Press Power Button RTC – Motorola MC146818A Real-time clock Two Key Functions: Keeping track of the time of day Storing system data Timings: RTC Battery 3V 32.768KHz crystal VccRTC active to RTCRST# inactive: T = 18ms H/W Design- -5 -6 -6 -7 AD_OFF AC Mode: AD+ - U2 Internal Diode(P-MOS) - DCBATOUT DC Mode: BT+ - U1 Internal Diode(P-MOS) - DCBATOUT BT+ Internal LDO to generate AUX Power DCBATOUT-5V/3D3V_AUX_S5 VREG5=4.5VVO1=0V, IREG5max=250mA VREG3=3VVO2=0V, IREG3max=250mA Switch over: If VO1=4.7V, 5V LDO Shut off, VREG5=VO1 If VO2=3.15V, 3V LDO Shut off, VREG3=VO2 -4 -5 TPS51125 The total value of all capacitors for Vreg3 need be 10uF. Capacitor for Vreg5 need be 27.5uF ~ 33uF. KBC WPCE773L 3D3V_AUX_S5 AC_IN# from Charge IC S5_ENABLE -4 -2 EC_RST# -3 HW_THRM_SHDN# G7921 S5_ENABLE Output Sequence: 3D3V_AUX_S5 Ready AC_IN# output from Charge IC, , when ACDET over 2.4V Crystal 32.768KHz stable BIOS/KBC code ready 5V_S5_EN -2 -1 -1 TP51125 generate 5V_S5 and 3D3V_S5 Power: DCBATOUT Power Ready S5_ENABLE output from KBC 5V_S5_EN 5V_S5_EN KBC RSMRST# Signal to KBC output from ICH9M Delay at least 10ms after 3D3V_S5