8-2时序逻辑电路设计.pptVIP

异步复位，同步预置和同步使能的通用计数器的设计。 Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity counter is Generic (size:integer:=8) Port(reset : in std_logic; set : in std_logic; enable : in std_logic; clk : in std_logic; cout : in std_logic; q : buffer std_logic_vector(size-1 downto 0) ); end counter; 第8章 基于VHDL基本数字电路设计 architecture rtl of counter is begin p1:process(clk,reset) begin if (reset=’1’) then q= (other=’0’); elsif (clk’event and clk=’1’) then if (set=‘1’) then q( other=’1’); elsif (enable=’1’) then q=q+1; else q=q; end if; end if; end process p1; end rtl; 异步复位，同步预置和同步使能的通用计数器的设计。 第8章 基于VHDL基本数字电路设计 LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY async_rdff IS PORT(d,clk,reset:IN std_logic; q,qb:OUT std_logic); END async_rdff; ARCHITECTURE rtl OF async_rdff IS BEGIN PROCESS(clk,reset) BEGIN IF (reset=‘0’) THEN q=‘0’; qb=‘1’; ELSEIF (clk’event AND clk=‘1’) THEN q=d; qb=NOT d; end if; End process; End rtl; 第8章 基于VHDL基本数字电路设计 LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY acount IS PORT(d,clk,reset:IN std_logic; q:OUT std_logic_vector(3 downto 0)); END acount; ARCHITECTURE rtl OF acount IS Component async_rdff PORT(d,clk,reset:IN std_logic; q,qb:OUT std_logic); END component ; Signal q_tmp: std_logic_vector(4 downto 0); BEGIN q_tmp(0)=clk; lable1: for I 0 to 3 generate Async_rdffx:async_rdff port map(q_tmp(i+1), q_tmp(i),reset,