EDA工具课程之PrimeTime讲解.ppt

Company Logo 六、实例分析 Company Logo 六、实例分析 clock MY_CLOCK (rise edge)???????????????????????????????????????????? 6.00?????? 6.00 clock network delay (ideal)??????????????????????????????????????????? 2.00?????? 8.00 clock uncertainty?????????????????????????????????????????????????????? -0.50?????? 7.50 S3/P3_reg_47_/CK (DFFTRXL)???????????????????????????????????????????? 0.00?????? 7.50 r library setup time????????????????????????????????????????????????????? -0.28?????? 7.22 data required time?????????????????????????????????????????????????????????????????? 7.22 Critical Path终点的Flip-