Architecture (I).pptVIP

好像这个Min可以简化的。求B时，条件可以为：BC 注意减法运算的两个输入数据的顺序，被减数是从输入端B输入的。 事实上，算术运算部件是一个非常复杂的部件，但我们主要是分析CPU的整体设计，所以忽略ALU的细节 Combinational Circuits Acyclic Network of Logic Gates Continuously responds to changes on inputs Outputs become (after some delay) Boolean functions of inputs Acyclic Network Inputs Outputs Bit Equality P272 Figure 4.9 Generate 1 if a and b are equal Hardware Control Language (HCL) Very simple hardware description language Boolean operations have syntax similar to C logical operations We’ll use it to describe control logic for processors Bit equal a b eq bool eq = (ab)||(!a!b) HCL Expression Bit-Level Multiplexor P273 Figure 4.10 Control signal s Data signals a and b Output a when s=1, b when s=0 Its name: MUX Usage: Select one signal from a couple of signals Bit MUX b s a out bool out = (sa)||(!sb) HCL Expression Word Equality P274 Figure 4.11 32-bit word size HCL representation Equality operation Generates Boolean value b31 Bit equal a31 eq31 b30 Bit equal a30 eq30 b1 Bit equal a1 eq1 b0 Bit equal a0 eq0 Eq = B A Eq Word-Level Representation bool Eq = (A == B) HCL Representation Word Multiplexor P275 Figure 4.12 Select input word A or B depending on control signal s HCL representation Case expression Series of test : value pairs Output value for first successful test Word-Level Representation HCL Representation b31 s a31 out31 b30 a30 out30 b0 a0 out0 int Out = [ s : A; 1 : B; ]; s B A Out MUX HCL Word-Level Examples P277, P276 Find minimum of three input words HCL case expression Final case guarantees match A Min3 MIN3 B C int Min3 = [ A B A C : A; B A B C : B; 1 : C; ]; D0 D3 Out4 s0 s1 MUX4 D2 D1 Select one of 4 inputs based on two control bits HCL case expression Simplify tests by assuming sequential matching int Out4 = [ !s1!s0: D0; !s1 : D1; !s0 : D2; 1 : D3; ]; Minimum of 3 Words 4-Way Multiplexor OF ZF SF OF ZF SF OF ZF SF OF ZF SF Arithmetic Logic Unit P278 Figure 4.13 Combinational logic