Sparc Architecture Overview.pptVIP

Natawut Nupairoj Assembly Language First Semester 2542 Assembley Language Natawut Nupairoj Sparc Architecture Overview Von Neumann Architecture Designed by John von Neumann in 1949. Machine = CPU + Memory Program is stored in memory along with data. CPU has Program Counter (PC) and Instruction Register (IR) Use PC to keep the current location of instruction being executed. Von Neumann Architecture Control unit fetches an instruction from memory (located by PC) and stores in IR. Memory = Memory Address Register (MAR) + Memory Data Register (MDR) CPU puts an address in MAR and load/store from/to MDR. Machine Organization Diagram Instruction Execution Fetch-Decode-Execute cycles: Fetch the next instruction from memory. Change PC to point to next instruction. Determine the type of the instruction fetched. Find where the data being used by the instruction is kept. Fetch the data, if required. Execute the instruction. Store the results in the appropriate place. Go to step 1 and start all over again. Instruction Cycles pc = 0; do { ir := memory[pc]; { Fetch the instruction. } pc := pc + INSTR_SIZE; { Move PC to next instruction. } decode(ir); { Decode the instruction. } fetch(operands); { Fetch the operands. } execute; { Execute the instruction. } store(results); { store the results. } } while(ir != HALT); Sparc Architecture Overview Load/Store architecture ALU cannot access data from memory directly. Data must be loaded into registers before computing. RISC (Reduced Instruction Set Computer) architecture All instructions are one word (32 bits). 5-stage Pipelining CPU. Sparc Registers There are 32 registers (%r0 - %r31). Each register is 64-bit for UltraSparc (128-bit for UltraSparc III). Registers are logically divided into 4 sets:global (%gx), in (%ix), local (%lx), and out (%ox). All registers are equal, can perform any operations. Special register: %g0 (%r0) - always discards writes and return zero. Sparc Registers Global %g0 %r0 readonly / return zer