第二章Blackfin处理器及BF60x3r(电子科技大学)详解.ppt

DMA_XCNT值是传送所需要的整个工作单元的DMA_CFG.MSIZE的数 对于一个完整的线性缓冲传输，DMA_XMOD由所选择的DMA_CFG.MSIZE确定。 为使能DMA通道，DMA_CFG.FLOW必须设置STOP模式。DMA_CFG.WNR必须配置成存储器读操作，DMA_CFG.PSIZE必须配置成不大于外设的DMA总线所支持的总线宽度。 * * * * * * * * 对比没有60的数据 这个表示如果在BF60x上进行上面的那些处理，节省了这么多开销，也就是说BF60x上用硬件来做，开销近似于0 * * * RCU: Reset Control Unit * 引导有两类 Master mode：DSP主动加载外部的存储器 Slave Mode：DSP接收外部主控器件发送的数据 The removable storage interface (RSI) controller is a fast, synchronous peripheral that uses various protocols to communicate with MMC, SD, and SDIO cards. The RSI is compatible with the following protocols. ? MMC (Multimedia Card) bus protocol ? SD (Secure Digital) bus protocol ? SDIO (Secure Digital Input Output) bus protocol * * CGU：clock generation unit * CGU：clock generation unit PLLClk: PLL clock,为所有时钟提供源 CCLK: core clock，CCLK0为Core 0时钟，CCLK1为Core 1时钟 SYSCLK: system clock，为系统总线及SCLK0和SCLK1提供时钟源 SCLK0为PVP和所有非SCLK1的外设提供时钟， SCLK1为SPORT、SPI、ACM（ADC control module）外设提供时钟 DCLK :LPDDR or DDR2 RAM Clock OCLK:Output clock * CGU_STAT寄存器 typedef enum { ADI_PWR_CLK_STAT_PLL_EN = BITM_CGU_STAT_PLLEN, /* The PLL Enable setting. */ ADI_PWR_CLK_STAT_PLL_BYPASS = BITM_CGU_STAT_PLLBP, /* The PLL Bypass setting. */ ADI_PWR_CLK_STAT_PLL_LOCKED = BITM_CGU_STAT_PLOCK, /* The PLL Lock setting. */ ADI_PWR_CLK_STAT_CLK_ALIGN = BITM_CGU_STAT_CLKSALGN, /* The Clock Alignment setting. */ ADI_PWR_CLK_STAT_CCLK0_BUFF_EN = BITM_CGU_STAT_CCBF0, /* The CCLK0 Buffer Status setting. */ #if defined (__ADSPBF609_FAMILY__) ADI_PWR_CLK_STAT_CCLK1_BUFF_EN = BITM_CGU_STAT_CCBF1, /* The CCLK1 Buffer Status setting. */ ADI_PWR_CLK_STAT_SCLK0_BUFF_EN = BITM_CGU_STAT_SCBF0, /* The SCLK0 Buffer Status setting. */ ADI_PWR_CLK_STAT_SCLK1_BUFF_EN = BITM_CGU_STAT_SCBF1, /* The SCLK1 Buffer Status setting. */ #endif ADI_PWR_CLK_STAT_DCLK_BUFF_EN = BITM_CGU_STAT_DCBF, /* The DCLK Buffer Status setting. */ ADI_PWR_CLK_STAT_OUTCLK_BUFF_EN = BITM_CGU_STAT_OCBF,