vHDL用jk触发器设计异步四位二进制假发计数器.docVIP

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SCAN_LED IS PORT ( d : IN STD_LOGIC_VECTOR(3 DOWNTO 0); SG :OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END; ARCHITECTURE al OF SCAN_LED IS BEGIN process(d) begin CASE d IS WHEN 0000 = SG = 0111111; WHEN 0001 = SG = 0000110; WHEN 0010 = SG = 1011011; WHEN 0011 = SG = 1001111; WHEN 0100 = SG = 1100110; WHEN 0101 = SG = 1101101; WHEN 0110 = SG = 1111101; WHEN 0111 = SG = 0000111; WHEN 1000 = SG = 1111111; WHEN 1001 = SG = 1101111; WHEN 1010 = SG = 1110111; WHEN 1011 = SG = 1111100; WHEN 1100 = SG = 0111001; WHEN 1101 = SG = 1011110; WHEN 1110 = SG = 1111001; WHEN 1111 = SG = 1110001; WHEN OTHERS = NULL ; END CASE ; end process ; END al;