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1、优先级编码器。图是一个7级优先级编码器。如果输入矢量中出现多个1，那么电路将优先对最高位编码输出。000表示输入矢量中没有出现位1，不需要编码输出。使用WHEN/ELSE语句实现该电路。 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY encoder IS PORT ( x: IN bit_VECTOR(7 DOWNTO 1); y: OUT bit_VECTOR(2 DOWNTO 0)); END encoder; ARCHITECTURE encoder1 OF encoder IS BEGIN y = 111 WHEN x(7)=’1’ELSE 110 WHEN x(6)= ’1’ ELSE 101 WHEN x(5)= ’1’ ELSE 100 WHEN x(4)= ’1’ ELSE 011 WHEN x(3)= ’1’ELSE 010 WHEN x(2)= ’1’ ELSE 001 WHEN x(1)= ’1’ ELSE 000 ; END encoder1; 2、编写实现如图所示状态转移关系的VHDL代码。 library ieee; use ieee.std_logic_1164.all;entity fsm is port( inp,rst,clk:in std_logic; outp:out std_logic_vector(1 downto 0)); end fsm; architecture arch of fsm is type state is(state1,state2,state3,state4); signal pr_state,nx_state:state; signal temp:std_logic_vector(1 downto 0); begin process(rst,clk) begin if(rst=1) then pr_state=state1; elsif(clkevent and clk=1) then outp=temp; pr_state=nx_state; end if; end process; process(inp,pr_state) begin case pr_state is when state1 = temp=00; if(inp=1) then nx_state=state2; else nx_state=state1; end if; when state2 = temp=01; if(inp=0) then nx_state=state3; else nx_state=state4; end if; when state3 = temp=10; if(inp=1) then nx_state=state4; else nx_state=state3; end if; when state4 = temp=11; if(inp=1) then nx_state=state1; else nx_state=state2; end if; end case; end process; end arch; 3、通用奇偶校验发生器电路 当输入矢量中1的个数分别为奇数和偶数时，所增加的输出位的值相应地为1和0，这样使得输出矢量中1的个数恒为偶数。 1 ------------------------------------------------- 2 ENTITY parity_gen IS 3 GENERIC (n: INTEGER := 7); 4 PORT ( input: IN BIT_VECTOR(n-1 DOWNTO 0); 5 output: OUT BIT_VECTOR(n D