VHDL状态机设计与应用研讨.pptVIP

【例8-8】 ARCHITECTURE behav OF AD0809 IS SIGNAL cs, SOUT: STD_LOGIC_VECTOR(4 DOWNTO 0 ); CONSTANT s0 : STD_LOGIC_VECTOR(4 DOWNTO 0) := 00000 ; CONSTANT s1 : STD_LOGIC_VECTOR(4 DOWNTO 0) := 11000 ; CONSTANT s2 : STD_LOGIC_VECTOR(4 DOWNTO 0) := 00001 ; CONSTANT s3 : STD_LOGIC_VECTOR(4 DOWNTO 0) := 00100 ; CONSTANT s4 : STD_LOGIC_VECTOR(4 DOWNTO 0) := 00110 ; SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN Q = REGL; ADDA = ‘0; PROCESS(cs,EOC) BEGIN --规定各状态转换方式 IF RST=‘1’ THEN cs=so; ELSIF CLK’EVENT AND CLK=‘1’ THEN CASE current_state IS