EDA实验(整理版)探析.doc

 PAGE \* MERGEFORMAT 14 数据选择器 MUX41A四选一 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux41a is port(EN,A1,A0,D3,D2,D1,D0:in std_logic; Y:out std_logic); end mux41a; architecture one of mux41a is signal A:std_logic_vector(2 downto 0); begin A=ENA1A0; Y=D0 WHEN A=000else D1 WHEN A=001ELSE D2 WHEN A=010ELSE D3; END ONE; MUX61A六选一 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux61a is port(D0,D1,D2,D3,D4,D5:in std_logic; A:std_logic_vector(2 downto 0); Y:out std_logic); end mux61a; architecture AA of mux61a is begin Y=D0 WHEN A=000 ELSE D1 WHEN A=001 ELSE D2 WHEN A=010 ELSE D3 WHEN A=011 ELSE D4 WHEN A=100 ELSE D5 WHEN A=101 ELSE Z; end AA; MUX441A四位四选一 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux441a is port(A:in std_logic_vector(2 downto 0); D3,D2,D1,D0:in std_logic_vector(3 downto 0); Y:out std_logic_vector(3 downto 0)); end mux441a; ARCHITECTURE ONE OF MUX441A IS BEGIN Y=D0 WHEN A=000ELSE D1 WHEN A=001ELSE D2 WHEN A=010ELSE D3; END ONE; 译码器 DEC38A 3-8译码器 library ieee; use ieee.std_logic_1164.all; entity DEC38A is port( A2,A1,A0:in std_logic; S1,S2,S3:in std_logic; Y:out std_logic_vector(7 downto 0)); end entity DEC38A; architecture one of DEC38A is signal S:std_logic_vector(5 downto 0); begin S=S1S2S3A2A1A0; with S select Ywhen 100000, when 100001, when 100010, when 100011, when 100100, when 100101, when 100110, when 100111, when others; end one; DEC_DISPLAY 共阴极数码管 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity DEC_DISPLAY IS port(A:in std_logic_vector(3 downto 0); EN:IN STD_LOGIC; Ya,Yb,Yc,Yd,Ye,Yf,Yg:OUT STD_LOGIC); end dec_display; architecture one of dec_display is signal s:std_logic_vector(4 downto 0); signal Y:std_logic_vector(6 downto 0); begin S=ENA; Ya=Y(6); Yb=Y(5); Yc=Y(4); Yd=Y(