3.2 MOS器件瞬态和无源器件.ppt

* 减小连线RC延迟的措施 合理的连线设计 优化的按比例缩小 多层互连技术 采用新的低阻连线材料 采用新的低k介质材料 * 铜互连和低k介质 本节总结 * MOS瞬态特性 集成电路中的电阻和电容 互连线 * A silicide is a compound material formed using silicon and a refractory metal to create a highly conductive material that can withstand high-temperature process steps without melting. WSi2 has a resistitivity of 130 microohms-cm Similar techniques are used to reduce the source and drain resistance of the transistor * From the Intel generations, its clear that the wires get closer together, but the vertical dimensions do not shrink proportionally, which increases capacitance. In contrast, IBM’s copper interconnect has much thinner layers – thus less capacitance – even though the wire resistance (including cladding) is similar to that of the P858 technology * plots the waveforms at different points in the wire as a function of time (and space), what is L? (cm length?) Observe how the step waveform “diffuses” from the start to the end of the wire and that the waveform rapidly degrades, resulting in considerable delay for long wires * For lecture Why is chain model important – because its what most resistive-capacitive wires look like in a digital circuit (encountered most often) Note - the shared-path resistance is replaced by the path resistance! If all Resistances are equal size can replace R values by Req * 互连线对电路的影响 互连线的延迟占据电路整体延迟的比例不断增加 互连线的IR电压降，引起信号电压幅度下降 芯片面积增大使连线长度增加，进一步加剧以上问题 * 模块 最大延迟时间(ps) Adder 600 Result Mux 60 Early Bypass Mux 100 Middle Bypass Mux 80 Late Bypass Mux 75 2mm wire 100 Itanium处理器的算术逻辑单元（ALU）结构图 如果触发器的建立时间为65ps,clk到输出Q的延迟时间为50ps 请计算电路工作的最大时钟周期 * 互连线 寄生电容 寄生电阻 寄生电感 互连线引起可靠性问题 互连线的RC延迟 * 连线的寄生电容 * 互连线电容 * 边缘效应 * 互连线寄生电容：特征尺寸减小 * 互连线 寄生电容 寄生电阻 寄生电感 互连线引起可靠性问题 互连线的RC延迟 * 连线的寄生电阻 连线电阻: R=R□L/W, R□=ρ/T 接触孔电阻: Rco = ρc/Wl * 不同连线材料的电阻率 材料 电阻率(Ω-m) 银(Ag) 1.6×10-8 铜(Cu) 1.7×10-8