毕业设计（论文）-基于FPGA的多功能数字钟设计.doc

摘??? 要 VHDL是Very High Speed Integrated Circuit Hardware Description Language的缩写,意思是超高速集成电路硬件描述语言。对于复杂的数字系统的设计,它有独特的作用。它的硬件描述能力强,能轻易的描述出硬件的结构和功能。这种语言的应用至少意味着两种重大的改变：电路的设计竟然可以通过文字描述的方式完成；电子电路可以当作文件一样来存储。随着现代技术的发展,这种语言的效益与作用日益明显,每年均能够以超过30%的速度快速成长。 本文介绍一种基于FPGA的数字时钟设计方法简要介绍了VHDL语言的一些基本语法和概念后,进一步应用VHDL,在MAX+plusII 的环境下设计一个电子钟,最后通过仿真出时序图实现预定功能。电子钟的时间显示用到了七段数码管(或称七段显示器)的电路设计,内部的时间控制输出则用到了各种设计,包括：时钟分频模块、计时模块、按键模块和显示模块四个部分。 关键词：VHDL,电子钟,七段显示器,时序图。1.1?Abstract ?? VHDL is an abbreviation for “Very High Speed Integrated Circuit Hardware Description Language”. and is along with Verilog the most widely used hardware description language. It is used to describe the behavior and structure of electronic systems, but is particularly suited as a language to describe the structure and behavior of digital electronic hardware designs. The application of it means two changes: electro circuit design can be done by the kind of file description.; and electro circuit can be stored as a file.It is used to lower the cost and reduce the design cycle. It can supply designers’ needs easily. With the development of modern technology it grows more than 30% every year. ?This graduation project content was was introducing briefly after VHDL language some basic grammars and the concept, further applied VHDL, designed an electron clock under the MAX+plusII environment, finally left the succession chart realization predetermined function through the simulation.The electron clock time demonstrated used seven sections of nixietubes (or called seven-segment displays) the circuit design, internal timing control lost the origin to use each kind of design, including: Clock frequency division module, time module, pressed key module and demonstration module four parts. Key words: Vhdl,electronic clock, seven segment display, time-analyse . 目 录 第一章 绪论 1 1.1 选题背景 2 1.1.1 课题相关技术的发展 2 1.1.2 课题研究的必要性 2 1.2 课题研究的内容 3 第二章 FPGA简介 4 2.1 FPGA概述 4 2.2 FPGA基本结构 4 2.3 FPGA系统设计流程 6 2.4 FPGA开发编程原理 8 2.5 Quartu