毕业设计（论文）-于VHDL语言的HDB3码的编码和译码.docVIP

PAGE PAGE \* MERGEFORMAT I 摘 要 伴随着集成电路技术的发展，电子设计自动化(EDA)逐渐成为重要的设计手段，已经广泛应用于模拟与数字电路系统等许多领域。EDA的一个重要特征就是使用硬件描述语言(VHDL)来完成设计文件。诞生于1982年的VHDL语言是经IEEE确认的标准硬件描述语言，在电子设计领域受到了广泛的接受。 数字基带信号的要求主要有两点，第一是对各种代码的要求，期望将原始信息符号编制成适合于传输用的码型；第二则是对所选的码型的波形的要求，期望波形适宜于在信道中传输。HDB3编码是数字基带信号传输中常用的传输码型，因其具有无直流成分，低频成分少和连零位数目最多不超过三个等明显的优点，对时钟信号的恢复十分有利而成为普遍使用的基带传输码之一。本设计是在Quartus II开发环境下采用VHDL语言的，设计HDB3编码器和译码器。根据编码规则将译码器分为三个部分：插V模块、插B模块、单极性变双极性模块。根据译码规则，译码器只包含一个模块。最后，对每个模块进行仿真，实现相应功能后再进行整体仿真。 关键词 HDB3 VHDL 编码 译码 PAGE PAGE \* MERGEFORMAT 38 Abstract The Electronic Design Automation (EDA) technology has become an important design method of analog and digital circuit system growing. One important characteristic of the EDA As is the integrated circuit one of the standard description languages validated by IEEE， which was firstly introduced in 1982. And it was widely used by electronic designer now. The requirements of digital baseband signals are two points, The first is the requirement of various code, expected the preparation of the original information symbols used to pattern in a form suitable for transmission; The second is the requirements of the pattern of the selected waveform, expected waveform suitable for transmission in the channel.The HDB3 coding scheme is commonly used in digital baseband transmission .The HDB3 code ，which has features of zero DC bias via alternating positive-negative voltage level bit by bit and no more than three continuous-zero bits ， deduces the power dissipation and makes the receiving device easy to recover the clock in the transmitted code stream .so my major content of graduated design is designing based on the HDB3 volume/decoder of VHDL language， the requirement that it will reach is the basic skill that can realize HDB3 volume/decoder function in software can， and can coordinate entire design， make sure it reach the requirement that anticipated. This design in Quartus II development environment uses VHDL language to design HDB3 encoder and d