嵌入式系统硬件设计SI基础材料分析.pptx

嵌入式系统硬件设计SI基础 前言 现代电路设计不断朝高速、高密度、低电压、大电流趋势发展，信号完整性（Signal Integrity，SI）、电源完整性（Power Integrity，PI）和电磁兼容（Electromagnetic Compatibility，EMC）问题日益突出。传统设计方法显得力不从心，需综合三者间相互影响进行协同设计. SI挑战 SI问题是电路高速化的产物，电路高速化指电路中信号的有效带宽增加，主要表现在系统工作频率提高和数字信号边沿率加快两方面。高速电路常见的SI问题包括：反射（Reflection）、串扰（Crosstalk）、同时开关噪声（SSN，Simultaneous Switching Noise）、时序错位与抖动（Timing Skew Jitter）等 SI挑战 A digital signal Frequency 50MHz Risetime 1ns ( 10% - 90% ) Falltime 1ns ( 10% - 90% ) Bandwidth 350MHz Spectrum of a single pulse 10 ns risetime 1 ns risetime Spectrum of a pulse train The effect of missing harmonics 1st harmonic only 1st and 3rd harmonic only 1st to 5th harmonic 1st to 21st harmonic 反射 Signal integrity (SI) issue Interconnect + + + + + + - - - - - - - I(z,t) I(z,t) VG ZG ZL Transmission line Load Thevenin generator z 0 L The voltage and current on each point of the line is superposition of a forward and backward voltage, travelling in opposite directions. The voltage at each point of the line depends on the reflection coefficient at each line terminals: Transient behavior of voltage at each line terminals: At generator side (input): At generator side (input): Complex transient behavior related to the reflection coefficient on each extremities and transmission line discontinuities 反射解决方法 反射问题主要通过端接匹配解决，使信号在传输过程中感觉不到瞬态阻抗突变。 抖动-实际信号与理想信号间的时序波动，由系统内在噪声和外在噪声共同引起。 串扰 串扰-串扰是指多信号网络间边缘场耦合效应导致的噪声干扰现象。 串扰 高速电路中需要控制串扰的布线网络主要包括：高速并行总线、高速时钟总线、高速接插件等。常用的减小串扰措施包括：减小平行走线长度、增大线间距、采用平面作返回路径、减小互连特性阻抗以及采用防护布线等。 Basic transmission line Driver Transmission line Termination resistor The four describing parameters R Resistance per unit length [ohm / m] C Capacitance [ F / m ] L Inductance [ H / m] G Conductance [ S / m ] Impedance ( Z0 ) Impedance is measured in Ohms Impedance describes the AC resistance a driver will see when driving a signal into a indefinitely long transmission line. Z 0 = R + L j ? G + C j ? For a loss less line this simplifies to: Z 0 = L C [ohm] ? ? [ohm] Loss ( a ) Loss