Lec06(第六节).pptVIP

Digital Logic Design and ApplicationJin YanhuaLecture #6 CMOS Dynamic Electrical Behavior Other CMOS Input and Output Structures UESTC, Spring 2012 答疑安排 答疑地点： A教2楼教师休息室 电梯/(A202)旁边 答疑时间： 周二中午 1：00-2：00 周二7、8节 周四3、4节 周五3、4节 高性价比手机选购 Last Time 3.5 CMOS Steady-State Electrical Behavior Logic Levels and Noise Margins 30%VCC ? 0.1V Last Time Circuit Behavior with Resistive Loads The load is specified in terms of current. 例：P177 3.27 The load make the output voltage deteriorate. Ensure the sourcing and sinking current within specifications. Last Time Circuit Behavior with Nonideal Inputs The output voltage away from the power-supply rail. Output current ?, Power Consumption? Last Time Fanout The sum of the IIL(IIH) values of the driven inputs may not exceed IOLmax (IOHmax) of the driving output Need to do Thevenin-equivalent calculation for non-gate loads (LEDs, termination resistors, etc.) Effects of Loading Unused Inputs Never be left unconnected 3.6 CMOS Dynamic Electrical Behavior Both the speed and the power consumption of a CMOS device depend to a large extent on dynamic characteristics of the device and its load. Speed depends on two characteristics: Transition Time (转换时间) Propagation Delay (传播延迟) ≡ time that output takes to change states ≡ time from input changing to output changing 3.6.1 Transition Time Depend on two factors: “On” resistance of transistor Stray capacitance (寄生电容) In real digital circuit, the transition time approximately equals the RC time constant. 3.6.1 Transition Time tr tf tr tf HIGH LOW VIHmin VILmax 3.6.2 Propagation Delay ≡ time from input changing to output changing 3.6.3 Power Consumption PT : the partial short-circuiting of the CMOS output structure PL : the capacitive load on the output Static/Quiescent Power Dissipation Dynamic Power Dissipation 3.7 Other CMOS Input and Output Structures 1. Transmission Gates When EN=0, EN_L=1, the transistors are “off”, A and B are disconnected. Wh