基于dsp builderfir滤波器设计及仿真.pptVIP

Design for the fir filter based on dsp builder Dsp builder profile and basic design process Fir design process and something need to pay attention Dsp builder profile dsp builder is a system-level (or algorithm-level) design tools,it is on the top of multiple software ,it connects system level (algorithm simulation modeling) and RTL-level (hardware) two design tools together and places them in the Matlab / simulink graphic design platform，the QuartusII as the underlying design tools is set background，to play the greatest advantage of variety tools. Dsp builder basic design process 1、design model in Simulink : call dsp builder and other graphical modules in the Simulink libraries to constitute algorithm-level design or system-level design block diagram. 2、System Simulation in Simulink : use Simulink graphical simulation、analysis function to analysis this model correctness. 3、Dsp Builder completes VHDL conversion、compile、synthesis 、fitter:use SignalCompiler to convert the Simulink model files (. Mdl) into a common hardware description language, VHDL files . 4 、RTL-level simulation in Modelsim 5、timing simulation in QuartusII Fir design process The most basic fir filter can be expressed as: In which x (n) is the input sample sequence, h (n) is the filter coefficient, L is the order of the filter, y (n) is the filters output sequence. Fir design process For the fourth order fir filter can be expressed as y(n)=Cq[h(0)x(n)+h(1)x(n-1)+h(2)x(n-2)+h(3)x(n-3)+h(4)x(n-4)] Cq is quantization factor. For the direct I type fir filter can be cascaded, so we design a fourth order Fir filter first ,then generate the 16 order fir filter we want by cascading. Creating theFIR Model Creating the FIR Model Open simulink Library Browser by entering simulink in command window.you can also open simulink Library Browser by using the toolbar icon. Add the Dsp builder Block add the Dsp builder Block that you need into your model and double-click the block in yo