VHDL数字钟代码.docVIP

use ieee.std_logic_1164.all;--顶层实体，用的是20Mhz的时钟 use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity clock_shu is port clk : in std_logic; reset : in std_logic; duan : out std_logic_vector 5 downto 0 ; data_o : out std_logic_vector 7 downto 0 ; end; architecture a of clock_shu is component count60 port carry : std_logic; rst : std_logic; times : out integer range 0 to 59; full : out std_logic ; end component; component count24 port carry : in std_logic; rst : in std_logic; times : out integer range 0 to 23 --full : out std_logic ; end component; component i60bcd port interg : in integer range 0 to 59; ten : out std_logic_vector 7 downto 0 ; one : out std_logic_vector 7 downto 0 ; end component; component i24bcd port interg : in integer range 0 to 23; ten : out std_logic_vector 7 downto 0 ; one : out std_logic_vector 7 downto 0 ; end component; signal carry1,carry2 : std_logic; signal abin1,abin2 : integer range 0 to 59; signal abin3 : integer range 0 to 23; signal clk_1h : std_logic; signal sh,sl,mh,ml,hh,hl : std_logic_vector 7 downto 0 ; signal cnt : integer range 0 to 5 : 0; begin process clk --分频为1hz constant counter_len:integer: 1座机电话号码; variable cnt:integer range 0 to counter_len; begin if clkevent and clk 1 then if cnt counter_len then cnt: 0; else cnt: cnt+1; end if; case cnt is when 0 to counter_len/2 clk_1h 0; when others clk_1h 1; end case; end if; end process; process clk variable cnt1 : integer range 0 to 200; variable cnt2 : integer range 0 to 10; begin if clkevent and clk 1 then if cnt1 200 then cnt1: 0; if cnt2 10 then cnt2: 0; if cnt 5 then cnt 0; else cnt cnt+1; end if; else cnt2: cnt2+1; end if; else cnt1: cnt1+1; end if; end if; end process; process clk begin if clk 1 then case cnt is when 0 duan 000001;data_o sl; when 1 duan 000010;data_o sh; when 2 duan 000100;data_o ml; when 3 duan 001000;data_o mh; when 4 duan 010000;data_o hl; when 5 duan