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verilogcode /*******竞争冒险练习4思考两赋值比较，结果因机而异*************/ module ex1(clk,a,b,c); output [3:0] b,c; input [3:0] a; input clk; reg [3:0] b,c; always @(posedge clk) b=a; always @(posedge clk) c=b; always @(posedge clk) $display(ex1: a=%d,b=%d,c=%d,a,b,c); endmodule module ex2(clk,a,b,c); output [3:0] b,c; input [3:0] a; input clk; reg [3:0] b,c; always @(posedge clk) begin b=a; c=b; $display(ex2:a=%d,b=%d,c=%d,a,b,c); end endmodule `timescale 1ns/1ns module ex4test; wire [3:0] b1,c1,b2,c2; reg [3:0] a; reg clk; initial begin clk=0; forever #50 clk=~clk; end initial