s5pv210的系统时钟.docVIP

s5pv210系统时钟划分 划分成了三个domain（域） MSYS----main system DSYS-----display system PSYS-----periphreal system s5pv210时钟源 主时钟源---24MHz RTC时钟源--32768Hz HDMI时钟源--27MHz USB总线时钟---24MHz s5pv210时钟的关系 s5pv210的时钟参考值 时钟的倍频 硬件时钟（24MHz）------MSYS/DSYS/PSYS的主时钟：MOUT_MSYS/MOUT_DSYS/MOUT_PSYS 倍频参考值 倍频的寄存器 1）MOUT_MSYS倍频 计算公式： MOUT_DSYS和MOUT_PSYS倍频 计算公式： 时钟分频 程序代码 #define CLK_DIV0_MASK 0x7fffffff #define APLL_MDIV 0x7d #define APLL_PDIV 0x3 #define APLL_SDIV 0x1 #define MPLL_MDIV 0x29b #define MPLL_PDIV 0xc #define MPLL_SDIV 0x1 #define set_pll(mdiv, pdiv, sdiv) (131 | mdiv16 | pdiv8 | sdiv) #define APLL_VAL set_pll(APLL_MDIV,APLL_PDIV,APLL_SDIV) #define MPLL_VAL set_pll(MPLL_MDIV,MPLL_PDIV,MPLL_SDIV) //PCLK_PSYS = HCLK_PSYS/2 ;PCLK_PSYS=66MHz //HCLK_PSYS = MOUT_PSYS/5 ;HCLK_PSYS=133MHz //PCLK_DSYS = HCLK_DSYS/2 ;PCLK_DSYS=83MHz //HCLK_DSYS = MOUT_DSYS/4 ;HCLK_DSYS=166MHz //PCLK_MSYS = HCLK_MSYS/2 ;PCLK_MSYS=100MHz //HCLK_MSYS = ARMCLK/5 ;HCLK_MSYS=200MHz //SCLKA2M = SCLKAPLL/4 //ARMCLK = MOUT_MSYS ;ARMCLK =1000MHz void clock_init() { CLK_SRC0 = 0x0;//Select clock source 0 (Main) APLL_LOCK = 0x0000FFFF; //PLL locking period for APLL. MPLL_LOCK = 0x0000FFFF; //locking period for MPLL. //Set clock divider ratio 0 (System Clocks) CLK_DIV0 = ((128)|(424)|(120)|(316)|(112)|(48)|(44)|0); //Control PLL output frequency for APLL. //FOUT= MDIV * FIN / (PDIV*2^(SDIV-1)) = 0x7d*24/(0x3*2^(1-1))=1000 MHz APLL_CON0 = APLL_VAL; //MOUT_MSYS = 1000MHz //Control PLL output frequency for MPLL //FOUT = MDIV*FIN/(PDIV*2^SDIV)=0x29b*24/(0xc*2^1)= 667 MHz MPLL_CON = MPLL_VAL;//MOUT_DSYS = 667MHz, MOUT_PSYS =667MHz CLK_SRC0 = 0 }