哈工大模拟coms第15章版图汇编.pptVIP

Design of Analog Integrated Circuits Layout Outline 1. General Layout Considerations 2. Analog Layout Techniques 3. Substrate Coupling 15.1 General Layout Considerations Layout 15.2 Analog Layout Techniques 15.2.1 Multifinger Transistors 15.2.2 Symmetry 15.2.2 Symmetry 15.2.2 Symmetry 15.2.3 Reference Distribution 15.2.3 Reference Distribution 15.2.4 Passive Devices 15.2.4 Passive Devices 15.2.4 Passive Devices 15.2.4 Passive Devices 15.2.4 Passive Devices 15.2.4 Passive Devices 15.2.5 Interconnects 15.3. Substrate Coupling Substrate coupling effect Methods of minimizing the effect of substrate noise Methods of minimizing the effect of substrate noise Methods of minimizing the effect of substrate noise Methods of minimizing the effect of substrate noise Summary Layout Techniques Design rules:设计者与foundry的interface Symmetry Substrate Coupling Minimizing the effect of substrate noise Ground bounce * * 提纲 概述 设计规则：最小宽度、间距、包围、延伸 latchup、ESD、天线效应 模拟电路的版图技术 叉指晶体管可以降低S/D结面积和栅电阻； 设计时，栅电阻应小于其跨导的倒数；低噪中，栅电阻是1/gm的1/5到1/10 叉指数N↑→周边电容CP↑ 模拟电路的版图技术 模拟电路的版图技术 模拟电路的版图技术 模拟电路的版图技术 模拟电路的版图技术 Reduce mismatch 模拟电路的版图技术 Resistors 模拟电路的版图技术 Resistors NWELL电阻 模拟电路的版图技术 Resistors 工艺导致的变化±20%~ ± 30% 30000 20000 -1500 1000 N-well -500 500 1600 100 P+ diff -500 500 1500 70 N+ diff 50 50 200 30 P+ poly 50 50 -800 30 N+ poly BC [ppm/V] VC [ppm/V] TC ppm/°C 25°C R/? [W/?) Layer 模拟电路的版图技术 Capacitors big big ~1000 Junction capacitors 120 Poly-substrate 50~60 Metal-poly 30~40 Metal-substrate 30 20 50 Metal-metal 25 10 1000 Poly-poly (option) big huge 5300 Gate TC [ppm/°C] VC [ppm/V] Capa. [aF/mm2] Type 工艺导致的变化±5%~ ± 20% 模拟电路的版图技术 Inductors S W D P-silicon Substrate Oxide Via2 M2 M3 片上螺旋电感: D: 直径 W: 线宽 S: 间距 N: 圈数 参数: D, 决定于面积约束. W, S 和 N根据优化以下参数得到 Desired inductance L High quality factor Q High self-resonant frequency fSR 模拟电路的版图技术 Inductors D: 直径: D? – Q ? but fsr? as parasitic capacitance between substrate and the spiral increases. A good design usually has D 200 mm W: 线宽 Medal width sh