cadtopics.pptVIP

Verilog - * 6 always @(posedge clk) case (state) zero: begin out = 0; if (in) state = one1; else state = zero; end one1:  if (in) begin state = two1s; out = 1; end else begin state = zero; out = 0; end two1s:  if (in) begin state = two1s; out = 1; end else begin state = zero; out = 0; end default: begin state = zero; out = 0; end endcaseendmodule This is confusing: the output does not change until the next clock cycle Single-always Moore Machine (Not Recommended!) All outp