ARMMPCore体系结构性能增强功能.docxVIP

July 16–17, 2008Aoyama Diamond HallOmotesando, Tokyo, JapanARM MPCoreArchitecture Performance EnhancementSeminarJohn GoodacreSenior Program ManagerARM Processor Division1ARM Processor EvolutionSingle-issue, in-order, single bus transaction, no L2Nokia N810 using OMAP2420 with ARM1136 at 400MHzSingle-issue, in-order, multiple decoupled L2 transactionsNVIDIA Tegrawith ARM11 MPCore at 600-800MHzDual-issue, in-order, multiple integrated L2 transactionsT.I. OMAP3430with Cortex-A8 at 600-800MHz+(previously demo’ed at 1GHz)Multi-issue, out-of-order, multi-out-of-order bus transaction? Cortex-A9multicore capable2Designing for the Next GenerationA balance over the challenge of understandingWhat physical implementation can offer (MHz, power)The structure and layout of software (instruction mix, locality)The micro architecture of the processor (superscalar, OoO)The system in which the processor will exist (ram, mp, bus, DMA)Performance EstimationImplementation speed for a given processes geometry and flowProcessor micro architectureIntegration, memory and other system componentsEfficiency of processor on real-world workloadsPower EstimationPhysical IP and processes technologiesLow power design techniqueEffects on fabric interconnect and memory systemsAverage vs. typical vs. peak power consumption3ARM Cortex-A9? A new processor micro architecture with resources sized to matchthe increased software workload complexities of tomorrow’s software?Complex branch structures, increased level of DSP-like computation?Large amounts code and data memory with increasingly sparse locality? Plus multicore processing for scalable performance and reduced powerconsumption?ARM MPCore multicore technologySignoff Frequency830 MHz post STAwith ARMv7 MP Extensions(TSMC 65GP 32/32K L1)includes margins* and SIss, 0.99V, 125C (W/C freq.)? And enhanced system integrationPerformance2.50 DMIPS/MHz?Scalable multicore designPower (including RAMs)4.66DMIPS / mW?Advanced Bus InterfaceSilicon Area (core logic)