2014试卷库专英7.docVIP

三明学院《专业英语》试卷(7) （考试时间：90分钟） 使用班级： 学生数： 任课教师： 龚俊锋 考试类型 闭卷 题 序 一 二 三 四 五 总分 得 分 阅卷人 名词解释： Voltage reference transmission bandwidth waveform coding Spectral resolution frequency masking monophonic Procedural bit vector template Mechanism memory management interrupt latency Calculable scheduler RAM(random access memory) SR(silicon rectifier) SP(shift pulse) TP(temperature probe) PLD(phase-locked detector) RST(reset) PIO(parallel input output) DMM （digital multimeter） UUT（ unit under test） debug AWG（ arbitary waveform generator） 　PPM(pulse phase modulation) PRD(piezoelectric radiation detector) 　　PIN(positive intrinsic-negative) PID(proportional-integral-differential(controller)) RV(resistor with inherent variability dependent on the voltage) 二、阅读： Verilog and VHDL are the most popular languages for hardware description and modeling. Each hardware description language (HDL) models systems with discrete-event semantics that ignore idle portions of the design for efficient simulation. Both describe systems with structural hierarchy: a system consists of blocks that contain instances of primitives, other blocks, or concurrent processes. In addition, each HDL explicitly lists connections. Verilog provides more primitives geared specifically toward hardware simulation. On the other hand, VHDLs primitives are assignments such as a =b+c or procedural code. Verilog adds transistor and logic-gate primitives, and lets you define new primitives with truth tables. Both languages allow concurrent processed to be described procedurally. Such processes sleep until awakened by an event that causes them to run, read and write variables, and suspend. Processes may wait for a period of time(for example, #10in VErilog, wait for 10ns in VHDL), a value change (@(a or b), wait on a, b), or an event