基于FPGA的UART設计.docVIP

四川师范大学本科毕业设计 基于FPGA的UART设计 学生姓名 院系名称 专业名称 班 级 学 号 指导教师 完成时间 PAGE \* MERGEFORMAT II PAGE \* MERGEFORMAT II 基于FPGA的UART设计 电子信息工程专业 摘要： UART(通用异步收发器)是一种应用广泛，协议简单，易于调试的串行传输接口。FPGA是能高密度，低消耗完成所需要的逻辑功能的一种在线可编程器件，是现在业内提高系统集成度最佳技术之一，其可反复配置，且使用灵活。VHDL是描述电路功能或行为的一种硬件语言。本文首先阐述了运用FPGA实现UART接口的意义。接着介绍了UART的波特率发生器，发送功能和接收三大核心功能的理论知识。FPGA的工作原理，配置模式以及VHDL语言实现状态机的相关理论基础。给出了运用VHDL语言将UART三大功能嵌入在FPGA上的模块化设计方法。设计包括四大模块：顶层模块，波特率发生器，UART接收器，UART发生器。在FPGA片上集成UART主要功能，减少了电路板体积，同时电路也增加了可移植和反复配置功能，有效提高了电路的集成度和灵活性。最后运用Quartus ii 9.1实现了其功能仿真。 关键词：FPGA UART VHDL 有限状态机 The Design of Universal Asynchronous Receiver Transmitter Based on FPGA Abstract： UART (Universal Asynchronous Receiver Transmitter) is a widely used, simple protocol, easy to debug serial transmission interface. FPGA is capable of high-density, low-cost needed to complete a line of programmable logic devices, is now one of the industrys best technologies to improve system integration, which can be repeated to configure and use and flexible. VHDL description of the circuit function or behavior is a hardware language. This paper first describes the use of FPGA to realize the significance of the UART interface. Then introduced the theory of knowledge UART baud rate generator, sending and receiving three core functions. FPGA works, configuration mode and the VHDL-based state machine theory. Gives the UART using VHDL language to three functions embedded in the FPGA design. Design includes four modules: the top-level module, baud rate generator, UART receivers, UART generator. Integrated on-chip UART FPGA basic functions, reducing board space, the circuit also increases the portability and repeated configuration capabilities, improve the integration and flexibility of the circuit. Finally, the use of Quartus ii 9.1 implements its functional simulation. Key Words：FPGA ;UART ;VHDL;FSM PAGE \* MERGEFORMAT I PAGE \* MERGEFORMAT I 目 录 TOC \o 1-2 \h \u HYPERLINK \l _Toc16000 摘要： PAGEREF _Toc16000 I HYPERLINK \l _Toc14047