大学毕业设计—秒表的设计.docVIP

湖北理工学院 毕业设计[论文] 题 目：秒表的设计 院 系： 专 业： 姓 名： 指导老师： 摘 要 本系统由石英晶体振荡器、分频器、计数器、译码器、LED显示器组成，采用了中小规模集成芯片。总体方案设计由主体电路和扩展电路两大部分组成。其中主体电路完成数字钟的基本功能，扩展电路完成数字计时器的扩展功能，进行了各单元设计，总体调试。 数字计时器是由脉冲发生电路、计时和显示电路、清零电路、几部分组成的，电路由振荡器、分频器、计数器、译码器、显示器等元件构成。振荡器产生的脉冲信号经过分频器分频作用后为秒脉冲，秒脉冲送入计数器，计数器计数并且通过“时”、“分”、“秒”译码器显示时间。 本系统由计数器、译码器、LED显示器采用了中小规模集成芯片。总体方案设计由主体电路和扩展电路两大部分组成。其中主体电路完成循环显示的基本功能，扩展电路完成启动停止的扩展功能，进行了各单元设计，总体调试。 本文首先描述系统硬件工作原理，并附以系统结构框图加以说明，着重介绍了本系统模块的功能及工作过程,其次，详细阐述了程序的各个模块和实现方法。本设计以数字集成电路技术为基础。本文编写的主导思想是以硬件为基础，来进行各功能模块的编写。 关键词：石英晶体；分频器；计数器；译码器；脉冲 Abstract System has been composed of crystal oscillator , frequency divisionimplement , counter , decoder , LED display , has adopted to be hit by the small-scale integration chip. Two major part designing from main body circuit and expanding a circuit are composed of an overall plan. Main body circuits among them accomplish fundamental digital clock function , expand a circuit accomplishing the figure calculagraph expansion function, the element having carried out every designs that , population debugs. Figure calculagraph is to be composed of pulse generating circuit , circuit , zero clearing circuit , several parts reckoning by time and showing , the circuit is composed of components such as oscillator , frequency division implement , counter , decoder , display. The pulse signal that the oscillator produces counts and demonstrates time by time, mark, second decoder by that the frequency division implement frequency division effect queen being second of pulse , second of pulse sending in the counter , the counter. This system has adopt the middle small-scale integration chip from the counter , decoder , LED display. Two major part designing from main body circuit and expanding a circuit are composed of anoverall plan. Main body circuits among them accomplish the fundamental function that circulation demonstrates , expand a circuit accomplishing the starting sto